1. Field of the Invention
The present invention relates to an image capture apparatus having an image capture device for capturing images of a subject and a driving system for driving the image capture device.
2. Description of the Related Art
FIG. 1 is a circuit diagram of the circuit of an image capture device.
Photodiodes (hereinafter referred to as “PD sections”) 101 convert light into electrical charges (i.e., photoelectrical conversion) in accordance with the amount of exposure and accumulate the charges. Reference numeral 102 indicates floating diffusion sections (hereinafter referred to as “FD sections”). Upon the end of the accumulation, transfer gates (hereinafter referred to as “TXs”) 103 transfer the charges from the PD sections 101 to the corresponding FD sections 102 at the next stages. Reset gates (hereinafter referred to as “RSs”) 104 are used to reset the FD sections 102 and the PD sections 101. Floating diffusion amplifiers (hereinafter referred to as “FD amplifiers) 105 convert the charges, photoelectrically converted by the FD sections 102, into voltages. Selection gates (hereinafter referred to as “SELs”) 106 serve as selection switches for switching the reading of signals from the FD sections 102. For example, a typical digital camera has a pixel area including several millions of pixels, each defined by one PD section 101, one FD section 102, one TX 103, one RS 104, one FD amplifier 105, and one SEL 106.
A known operation of the image capture device shown in FIG. 1 will now be described.
First, before accumulation of charges, the PD sections 101 and the FD sections 102 are reset once. This is achieved by turning on the TXs 103 and RSs 104. Subsequently, when the TXs 103 and the RSs 104 are turned off, accumulation is started. At this point, since no charges are accumulated in the FD sections 102, first, the SELs 106 are turned, so that signals corresponding to that situation are read out to corresponding vertical output lines (V output lines) 125. As a result, reset noise levels are stored in corresponding circuit-module capacitors 108 provided in an S-n circuit block, the number of capacitors 108 being equal to the number of pixel columns.
When a predetermined amount of time has elapsed, the TXs 103 are turned on, so that the charges stored in the PD sections 101, which are buried photodiodes, are completely transferred to the corresponding FD sections 102 via the corresponding TXs 103. After read-out waiting time has elapsed, the SELs 106 are turned on, so that outputs corresponding to the accumulated charges are read out to the corresponding vertical output lines 125. Then, the signal levels of the outputs are stored in the capacitors 109 via corresponding switches 111. At this point, the reset levels and the signals levels are stored in the capacitors 108 and the capacitors 109, respectively. Thus, turning on read-out switches 115 and 116 to connect the reset levels and the signal levels to a differential amplifier 123 allows “pure” accumulation signals to be extracted.
In general, reset noises are first read, and then signals are read. When this sequence is reversed, while random reset noise cannot be completely eliminated, variations in gate-source voltages (Vgs) across the FD amplifiers 105 can be substantially cancelled. In a typical electronic-shutter mode, therefore, signals are first read, and then immediately, the FD sections 102 are reset again so that reset levels are read.
FIG. 13 illustrates how reading is performed in the image capture device. The upper three waveforms indicate the SELs 106, the RSs 104, and the TXs 103. Signals thereof may also be regarded as gate signals of the respective nMOS transistors of the SELs, 106, the RSs 104, and the TXs 103.
Graphics represented by a square 56 and a triangle 57 below the waveforms represent, in a time axis, an operation for each pixel row in the pixel area. Reference numeral 50 indicates a line at the upper side of the screen and 51 indicates a line in the lower side of the screen. At time 52, the TXs 103 and the RSs 104 are reset in a pulsed manner at the same time, so that the PD sections 101 and the FD sections 102 of all the pixels are simultaneously reset. After the reset is completed, charges generated in response to incident light are stored in the PD sections 101 of all the pixels. The square 56 represents charges being accumulated in the PD sections 101. Time 53 indicates the end of the accumulation. The horizontal length indicates accumulation time Tint. Since the charges in all the pixels are simultaneously transferred at the end of the accumulation, first, in order to ensure that the FD sections 102 contain no charges, the RSs 104 are turned on in a pulsed manner to reset the FD sections 102. Immediately after the reset, the TXs 103 are turned on in a pulsed manner to simultaneously transfer the charges of all the pixels.
At time 54, reading/scanning for each row is started. Time until charges in all the rows are read out refers to waiting time Twait. A vertical scan circuit 121 sequentially selects the rows, thereby performing the scanning/reading.
In a row selected by the SELs 106, signals (S) stored in the FD sections 102 in a waiting state are transferred and stored in the capacitors 108 in response to ON pulses PTS (pulses applied to switching transistors 110) indicated at reference numeral 58. Next, in order to cancel variations in gate-source voltages Vgs of the FD amplifiers 105, only the RSs 104 in the selected row are turned on, so that the FD sections 102 are reset, and pulses PTN go high (i.e., pulses are applied to the switching transistors 111), so that reset levels (N) are stored in the corresponding capacitors 109. After all signals of the pixels in the selected row are stored in the capacitors 108, the number thereof being equal to the number of horizontal pixels, in the S-n circuit (shown in FIG. 1), for example, a pair of horizontal-reading selection switches 117 and 118 are sequentially actuated to sequentially select the signals, for example, from the left-hand side to the right-hand side, for input to the differential amplifier 123. In this manner, outputs from all the pixels in the selected row are scanned and read.
When outputs of all the pixels in one row are scanned and read, the vertical scan circuit 121 selects the next row. Scanning, as described above, is repeated for all the rows, and at time 55, reading from the FD sections 102 ends. The triangle 57 represents a state in which the reading from the FD sections 102 is performed while the rows are scanned vertically, i.e., from the top to the bottom of the screen. A related example is disclosed in Japanese Patent Laid-Open No. 11-341363 (pages 10 to 18, FIG. 9).
In the known example, waiting time Twait, which is time until charges are read out, differs depending on the position of a row from the top of the screen. For example, since the top row is selected first in the row scanning, waiting time Twait therefor is substantially zero. On the other hand, since the bottom row needs to wait until reading of substantially all the rows is finished, waiting time Twait therefor becomes the longest. Since the PD sections 101 and the corresponding FD sections 102 are adjacent to each other, during the waiting period in which reading from the FD sections 102 is waited for, a certain percentage of light that enters the PD sections 101 leak into the adjacent FD sections 102. More specifically, this phenomenon will now be described with reference to the structure shown in FIG. 14.
FIG. 14 is a cross-sectional view of the vicinity of a PD section. Reference numeral 220 denotes a photodiode (PD section), which corresponds to a protection film. A photoelectric conversion portion is formed below the photodiode. Since the PD section 220 has a pn junction structure, photoelectrical conversion and charge accumulation are mainly performed at two junction portions, that is, between a P+ layer 221 and an N layer 222 and between the N layer 222 and a P well layer 223. The charge accumulation region of the PD section 220, which is defined by the P+ layer 221, the N layer 222, and the P well layer 223, is buried. This structure is called a buried photodiode, which prevents the penetration of noise charge from a surface layer, and is superior in that the amount of dark current is small. Reference numeral 224 is an N substrate, which is connected to a power supply. The P well layer 223 is connected to ground. When a voltage is applied to a transfer gate 226, charge is transferred from the PD section to an N+ FD section 225. Three layers are illustrated for aluminum wires 227. Since a CMOS sensor has a larger number of circuit elements in a pixel area than a CCD sensor, the amount of wiring is increased. The N+ FD section 225 corresponds to the gate of a MOS transistor serving as the FD amplifier, which is not shown in FIG. 14. Thus, in practice, the FD amplifier extends to a region outside FIG. 14 through the aluminum wire provided immediately above the FD section 225. Light that has traveled from a subject is supposed to reach the PD section 220 after passing through a microlens 229 and a color filter 228, but some of the light leaks into the FD section 225 through gaps between the aluminum wires 227, as indicated by a light beam 230. Further, even immediately below the PD section 220, some of charges 231, which have been photoelectrically converted, drift and leak into the FD section 225. This leakage also can be regarded as light leakage. As a result, the known technology has disadvantages. Specifically, depending on the waiting time, variations in light leakage within a screen increase the amount of noise that is introduced into image signals. Further, the brightness of a subject varies between the upper side and the lower side of the screen.